1. Field of the Invention
The present invention relates in general to a synchronous dynamic random access memory (referred to hereinafter as DRAM) having a plurality of cell banks, and more particularly to a hidden self-refresh method and apparatus for the synchronous DRAM in which self-refresh operations of the plurality of cell banks are individually controlled to enhance an operation speed of the synchronous DRAM.
2. Description of the Prior Art
Generally, a DRAM device comprises a plurality of cells, each of which consists of a capacitor for storing an electric charge therein and transistor for opening and closing charging and discharging paths of the capacitor. The electric charge stored in the capacitor is discharged little by little through a cell plate and the like with the lapse of time. For this reason, in the DRAM device, the DRAM cell must periodically be refreshed to make up for the electric charge into the cell capacitor.
In order to refresh the DRAM cell, a RAS only refresh method has been employed at the beginning. Thereafter, a CAS before RAS refresh method and a self-refresh method have recently been employed. Each of the CAS before RAS refresh method and the self-refresh method allows a chip to determine a refresh address for itself using an on-chip address counter.
However, the above-mentioned refresh methods all require a specified clock sequence from the outside to switch a present mode to a refresh mode. Also, the input and output are generally at an idle state for a time period that the refresh operation is performed. These result in a difficulty in a high-speed operation of the DRAM device. Further, in the case of a highly integrated memory device, a long refresh cycle is required for an effective operation of a chip. This long refresh cycle may degrade a reliability of the memory device since it comes to a limit of a cell data retention time.
For example, a conventional self-refresh apparatus will hereinafter be described briefly with reference to FIG. 1. As shown in FIG. 1, the conventional self-refresh apparatus comprises four cell banks 10-13 and four decoders 20-23 connected respectively to the four cell banks 10-13 to drive selectively row cell arrays thereof. The conventional self-refresh apparatus also comprises a self-refresh oscillator/timer circuit 40 for generating a clock signal, a refresh counter 50 for generating a refresh address signal in response to the clock signal from the self-refresh oscillator/timer circuit 40, and a row address latch circuit 70 for temporarily storing an external row address signal. Further, the conventional self-refresh apparatus comprises an address multiplexer 60 for selecting either the refresh address signal from the refresh counter 50 or the external row address signal from the row address latch circuit 70, and four row address buffers 30-33 for buffering the address signal selected by the address multiplexer 60 and applying the buffered address signal to the four decoders 20-23, respectively.
In operation, in a data access mode, the address multiplexer 60 transfers the external row address signal A0-An from the row address latch circuit 70 to the four decoders 20-23 through the four row address buffers 30-33, respectively. Each of the four decoders 20-23, when the external row address signal A0-An has a logical value addressing the cell bank connected thereto, drives a corresponding one of the row cell arrays in the addressed cell bank.
In a self-refresh mode, the address multiplexer 60 transfers the refresh address signal from the refresh counter 50 to the four decoders 20-23 through the four row address buffers 30-33, respectively. Each of the four decoders 20-23, when the refresh address signal has a logical value addressing the cell bank connected thereto, drives a corresponding one of the row cell arrays in the addressed cell bank.
The self-refresh oscillator/timer circuit 40 and the refresh counter 50 are driven only in the self-refresh mode to generate the clock signal and the refresh address signal, respectively. In the data access mode, the refresh counter 50 maintains its initial state and the self-refresh oscillator/timer circuit 40 generates no clock signal.
However, the above-mentioned conventional self-refresh apparatus has a disadvantage in that the data access operation cannot be performed in the refresh mode because the row address signal is applied in common to the cell banks 10-13 and the self-refresh oscillator/timer circuit 40 and the refresh counter 50 are driven only in the refresh mode. In other words, the data access operation cannot be performed in the refresh mode since the switching of the refresh mode and the data access mode is controlled by a row address strobe signal and a column address strobe signal from the outside and, furthermore, the external address signal cannot be inputted to the row address latch circuit in the refresh mode. Also, when the refresh mode is stopped, the refresh counter 50 is initialized, resulting in a loss of data stored in the row cell arrays which are not addressed. In result, the above-mentioned conventional self-refresh apparatus cannot enhance a data access speed of the DRAM device.